# Method and apparatus for efficient preamble detection in digital data receivers

Traditional techniques for data reception in burst-mode receivers are of significant complexity. To aid detection, most burst-mode systems transmit a preamble, or predetermined data pattern, at the start of each new block of data. Using current methods, the detection of a new preamble, indicating the arrival of a new burst of data, is particularly complex. A method and apparatus is disclosed that significantly reduces this detection complexity, while maintaining superior signaling performance. This simplification can lead to higher data throughput within processing-limited receivers, and/or a greater degree of parallelism in multiple channel receivers.

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**Description**

**CROSS-REFERENCE TO RELATED APPLICATIONS**

This application claims priority to the U.S. Provisional Application No. 60/504,171 filed Sep. 18, 2003,all of which is incorporated herein in it's entirety by this reference thereto.

**BACKGROUND OF THE INVENTION**

1. Technical Field

The invention relates to digital communications. More particularly, the invention relates to a method and apparatus for efficient preamble detection in digital data receivers.

2. Description of the Prior Art

Data communications systems may generally be grouped into two basic forms: continuous data communications systems, and discontinuous, or burst data communication systems. In burst systems, a block of data is sent over a finite period of time, and then transmission is halted until a later point in time. To aid in the recovery of data bursts, most burst-mode systems use a preamble, which is a predefined data pattern that is sent prior to the data to be communicated. It is well understood that the efficiency of detecting this unique preamble pattern is of utmost importance because the complexity of preamble detection has a major impact on overall receiver complexity. The invention described herein is concerned with identifying a reduced-complexity method of preamble detection in burst-mode data transmission systems.

Another method of classifying data communications is between synchronous and asynchronous communications systems. In synchronous systems, the transmitter and the receiver use some means to communicate symbol timing information, in addition to the data to be transmitted. Because the addition of symbol timing information necessarily mandates increased channel bandwidth, many data communications systems use asynchronous data communication. In an asynchronous system, the receiver must perform symbol timing recovery to identify the optimum signal phase at which to recover the received data. The invention herein disclosed focuses upon asynchronous burst-mode systems.

A wide variety of modulation techniques have been created to communicate digital data asynchronously. One of the most commonly used is known as Quadrature Phase Shift Keying, or QPSK. In QPSK and its variants, two bits of information are transmitted every symbol interval. Changes in the phase of the transmitted signal are used to communicate information. This is performed by modulating two independent waveforms, historically known as I and Q, onto a single carrier. *a *shows a representative constellation diagram of a transmitted QPSK signal, where the I and Q axes are plotted together to demonstrate how two bits of information represent four distinct signal phase states in QPSK. To recover this signal, a receiver must estimate which of the four phases was transmitted during each symbol interval. To prevent interference between the two modulating waveforms, a 90-degree fixed phase shift is introduced between I and Q during the modulation process. This phase shift makes it possible to recover the I and Q information independently, despite the use of a single transmission carrier. Throughout this document, QPSK modulation is used as an example to illustrate the core concept of the invention, but the concept may be applied to a wide variety of different modulation formats.

In any asynchronous communications system that uses carrier-based modulation such as QPSK, there is an incommensurate relationship between the frequency of the transmitted carrier and the frequency of the receiver. Physical component limitations always lead to a finite frequency error between the two devices. FIG. **1***b *shows the consequence of a typical frequency error. As indicated, the constellation diagram actually rotates over time, making it more difficult for the receiver to identify the signal phase that was actually transmitted properly.

There are two primary techniques to correct for the signal impairment that is caused by frequency error. In the first method, the receiver performs carrier frequency/phase recovery to correct for the rotation prior to making a symbol decision. Receivers that use this technique are said to use coherent detection. In the second method, the absolute phase of the received signal is deemed to be irrelevant. The transmitter instead performs differential encoding to allow the relative phase difference between sequential symbols to convey information. Receivers that rely solely upon differential phase to recover the transmitted signal phase are said to use differential detection. Note that it is possible for a receiver to use both of these methods simultaneously. If so, the result is known as coherent detection of a differentially encoded signal. This combination is very commonly used because the process of performing carrier recovery on a QPSK signal inevitably leads to a 90 degree phase uncertainty. The carrier recovery logic in a coherent receiver can lock on to any of four different absolute signal phases. By using differential encoding, the absolute phase ambiguity is irrelevant because only relative phase changes encode signal information.

Once a receiver has completed preamble detection, symbol timing recovery and carrier frequency/phase recovery, it then must demodulate the incoming signal to transform it from a waveform representation into digital data bits. As mentioned previously, this entails identifying which of the four possible QPSK waveform states were most likely sent by the transmitter during each symbol interval. During demodulation, the I and Q waveform values are often treated as a single complex number, and hence may be plotted as shown in *a *in constellation diagram form, with I and Q forming the real and imaginary components of the input sample values.

The theoretically optimum technique for coherent demodulation of a QPSK signal performs a Euclidean distance search between the complex received sample values and each of the four ideal QPSK states. The QPSK state having the shortest distance to the sample value is declared to be the received symbol value. For efficiency, most QPSK systems incorporate a fixed 45-degree rotational offset for the four ideal phase points, such that the QPSK signaling states are located at phases of 45 degrees, 135 degrees, 225 degrees, and 315 degrees. In this case, the complex Euclidean distance search may be replaced with a simple sign() comparison for the I and Q values.

In the case of pure differential detection, the theoretically optimum demodulation technique multiplies the complex received sample values by the complex conjugate of the signal as delayed by one symbol time. The resulting product represents a differential phase sample that indicates the relative phase from the previous symbol to the current symbol. Stated more precisely, given an input sample stream R_{k}, the complex differential phase sample Z_{k }is computed as:

*Z*_{k}*=R*_{k}*·R**_{k-N } (1)

where N is the number of samples that are acquired by the receiver per symbol time, and R*_{k-N }is the complex conjugate of the previous symbol's sample value. Note that this phase sample may also be considered a vector, with the (0,0) origin as the assumed initial endpoint. Once the differential phase vector has been computed, four separate complex derotations, corresponding to the negative value of the four ideal QPSK phases, are performed in parallel upon Z_{k}. The ideal phase derotation that results in the greatest positive magnitude is selected as the current symbol value (for example, see D. Divsalar, M. Simon, *Multiple*-*Symbol Differential Detection of MPSK, *http://d1.comsoc.org/cocoon/comsoc/servlets/GetPublication?id=147684; _{k}, one such technique is:

*x*=sign(real(*Z*_{k})+imag(*Z*_{k})) (2)

*y*=sign(real(*Z*_{k})−imag(*Z*_{k})) (3)

Depending on the signaling convention used by the specific implementation, the values of x and y correlate directly with the two data bits that underlie each symbol's QPSK state, yielding two bits of recovered information per symbol time.

It is important to point out one additional processing step that is performed by nearly all burst receivers, and that is the computation of the received signal's input power level. Signal power is important for many reasons for example, some devices display the signal power in the form of a logarithmic received signal strength indicator, while others compute the Signal/Noise Ratio of a signal as a quality metric by following the well-known power formula:

*SNR*(*dB*)=10* *log*_{10}((Signal Power)/(Noise Power)) (4)

where the signal power S and noise power N levels are computed by:

power_{k}=real(*R*_{k})^{2}*+imag*(*R*_{k})^{2 } (5)

Most burst mode receivers also require some form of signal power estimation during preamble detection. Without knowing the power level of the received signal, random noise may frequently yield false-positive preamble detection. While this is not harmful in and of itself, falsely triggering on noise can mask the start of subsequent data bursts, leading to a loss of valid data bursts. For this reason, signal power estimation is a very important element of most burst-mode data receivers.

It would be advantageous to provide a method and apparatus for efficient preamble detection in digital data receivers.

**SUMMARY OF THE INVENTION**

The presently preferred embodiment of the invention described herein describes new, highly-efficient approach to preamble detection. Beginning with an efficient implementation of a coherent preamble detector, an efficient differential preamble detector is described that is ideally suited for rapid burst detection. As a component of the invention, a new modulation power estimator is disclosed that can avoid the need for conventional power estimation. The invention applies both to hardware and software implementations, and can increase data throughput in existing processing-limited receivers, and/or increase the number of channels that may be supported in multiple-channel receiver implementations. Furthermore, extensions to other modulation formats, such as generalized MPSK or QAM, are apparent to those skilled in the state of the art. Thus, the inventive preamble detection mechanism herein described has broad potential applicability.

**BRIEF DESCRIPTION OF THE DRAWINGS**

*a *shows a representative constellation diagram of a transmitted QPSK signal, where the I and Q axes are plotted together to demonstrate how two bits of information represent four distinct signal phase states in QPSK;

*b *shows the consequence of a typical frequency error;

**DETAILED DESCRIPTION OF THE INVENTION**

To illustrate a presently preferred embodiment of the invention, **1** represent the reconstructed base band form of QPSK modulation. Carrier derotation block **2** aligns the incoming signal phases with the I and Q axes (controlled by means that are not relevant here), thus defining this as a coherent detector. Note, however, that no assumptions are made about symbol timing recovery.

Sign blocks **3***a *and **3***b *produce a ‘1’ if the I and Q samples are greater than or equal to 0, or a ‘0’ if the samples are less than 0, implementing coherent detection. Sample delay blocks **4***a *and **4***b *provide chains of N-sample delays, to yield one symbol-length delay for both I and Q. A differential decoder **5** combines the current symbol state with the prior symbol state to yield a differentially decoded symbol value. This decoder is typically implemented as a 16×2 bit lookup table in hardware, or as a 16-byte lookup table in software. The four inputs of the lookup table comprise two bits each from the current symbol and the previous symbol, and the output is a differentially decoded current symbol. A multiplexer **6** alternates between the least-significant and the most-significant bit of the differentially decoded symbol values, thus the binary data bits are clocked into a preamble shift register **7** at two bits/sample. The preamble shift register **7** therefore contains a serial-sequential representation of the received data stream. Because two samples are occurring per symbol, the length of shift register **7** is twice the number of bits in the preamble.

Conceptually, to locate a unique preamble data pattern using this shift register, the following expression may be used:

Preamble_Mismatch=Preamble_Register XOR PREAMBLE_PATTER (6)

where the PREAMBLE_PATTERN **8** is a bit-pair doubled representation of the unique data pattern that defines the implementation-specific value for the preamble. For example, a preamble data pattern of binary ‘0011001 1’ would yield a PREAMBLE_PATTERN of ‘000011110000111100001111’. Preamble_Mismatch indicates the outputs of the XOR gates **9**. These gates invert any bits in the preamble that should be a binary ‘1.’ When the outputs of the XOR gates **9** all become zero, indicating no mismatch, a data pattern has been identified that matches the desired preamble data pattern.

Next, it is necessary to implement a power estimation function. For this first preamble detector implementation, the power is computed using the traditional power function real(R_{k})·real(R_{k})+imag(R_{k})·imag(R_{k}). The multipliers **10***a *and **10***b *and the adder **11** compute the signal power. The signal power level is then compared by the comparator **12** to a predetermined minimum acceptable power threshold **13**. The power threshold **13** may be fixed, or it may be a variable threshold that is determined by other means that are related to recent noise or interference power levels. The output of the comparator **12** is a ‘1’ if the input signal level is too low to be considered a valid transmission, and it is ‘0’ if the power level exceeds the threshold. The output feeds the shift register **14**, i.e. the Power_invalid shift register, which contains a history of the invalidity status of recent samples.

To merge the Power_Invalid flags with the Preamble_Mismatch outputs, OR gates **15** effectively result in a product expression of:

Preamble_Status=Preamble_Mismatch OR Power_Invalid (7)

This effectively ensures that a candidate preamble has both the proper bit polarity, and the proper signal level. In addition, the OR gates **15** combine the I and Q data bits such that if either the I or Q samples has the incorrect signs, then the output of that sample's OR gate becomes true to indicate a non-matching symbol.

Thus far, no assumption has yet been made about the timing of the incoming samples with respect to the transmitted waveform, i.e. symbol timing recovery has been ignored. The two samples that are acquired per symbol interval may occur at any pair of signal phases that are offset from one another by 180 degrees. If the even signal samples are in approximate time-alignment with the transmitter, then the odd signal samples are exhibiting zero-crossings, and the odd outputs are not predictable. Alternately, if the odd signal samples are in approximate time-alignment with the transmitter, then the even sample outputs are not predictable. To resolve this problem, the AND gates **16** isolate N-1 out of N samples to ignore one sample/symbol during which zero-crossings may occur. With two samples/symbol, the AND gates **16** isolate alternate samples.

Once all of the relevant samples have the proper signs, and have been received with a sufficient power level, the output of the NOR gate **17** is driven high, indicating Preamble_Found **18**. At this point, the receiver begins the process of receiving the new data burst.

For clarity of presentation, **16** are not necessary in a hardware implementation of this preamble detector, though this function is appropriate for software-based parallel implementations. As a consequence, the AND gates **16** may be replaced with direct-wired connections to the NOR gate **17**, which thereby requires only four inputs in this example. Similarly, four OR gates **15** and eight XOR gates **9** may also be removed in the case of a two sample/symbol preamble detector.

It is possible to use this preamble detector with any integer number of samples/symbol, or any preamble length by extending the Shift Registers **7** and **14**, coupled with the appropriate number of XOR gates **9**, OR gates **15**, and AND gates **16**, and inputs to the NOR gate **17**. In any of these implementations, if the preamble used is an unchanging constant, then the XOR gates **9** may be eliminated, and NOT gates may be inserted selectively at any sample timing offset where the expected value of the preamble is ‘1.’

The embodiment of the invention illustrated by

Further Simplification

Throughout the following discussion, it will be assumed that the architecture of the receiver uses integer numeric representation (typically signed binary numbers), rather than floating point representation. This not only simplifies analysis, it is also representative of the majority of receiver implementations.

To identify opportunities for complexity reduction, it is helpful to examine a typical differential encoding scheme for QPSK data. To communicate a new symbol S_{k}, the transmitter selects a new relative carrier signal phase T_{k }based upon the following:

_{k}

_{k−N }to T

_{k}

Based upon this encoding, it is not surprising that the majority of documented systems use antipodal symbols to comprise the preamble, i.e. symbol values that are diametrically opposed to one another on the constellation diagram. Specifically, most QPSK preambles are comprised of various sequences of the symbol values 0 and 3, yielding phase changes of 0 degrees and 180 degrees. Furthermore, to simplify signal detection, T_{0 }is usually defined as an assumed phase of +45 degrees, or as +225 degrees. These initial phase points are chosen so that the I and Q waveform components of the transmitted signal simultaneously transition from a peak negative amplitude to a peak positive amplitude, or from a peak positive amplitude to a peak negative amplitude. This effectively aligns the preamble's antipodal symbol transitions with the signs of the coordinate axes. While the selection of antipodal symbols is normally made for reasons that are related to the bit error rate, this introduces an important opportunity for efficiency improvement.

Consider the first step in differential demodulation, which is to multiply a sample R_{k }by the complex conjugate of sample R_{k−N}, yielding differential phase sample Z_{k}. When expanded, this formula becomes:

real(*Z*_{k})=real(*R*_{k})·real(*R*_{k-N})−imag(*R*_{k})·−imag(*R*_{k-N}) imag(*Z*_{k})=real(*R*_{k})·imag(*R*_{k-N})+imag(*R*_{k})·real(*R*_{k-N}) (8)

Removing the double negation from the computation of real(Z_{k}) yields:

real(*Z*_{k})=real(*R*_{k})·real(*R*_{k-N})+imag(*R*_{k})·imag(*R*_{k-N}) imag(*Z*_{k})=real(*R*_{k})·imag(*R*_{k-N})+imag(*R*_{k})·real(*R*_{k-N}) (9)

The expression for real(Z_{k}) is particularly interesting in the context of antipodal signaling. Because this is a coherent detector, carrier rotator **2** has previously aligned the incoming I and Q sample values with the ideal state of the I and Q axes, with the exception of the previously-mentioned four-phase timing ambiguity. When the carrier detection loop has locked on to the improper signal phase, there are two potentially deleterious effects. First, at two of the three possible incorrect phase points, the signs of the I and/or Q samples are systematically incorrect. Second, at one possible phase offset, there is an apparent systematic swap of the I and Q values throughout the duration of the data burst.

Initially, to simplify the following analysis, the effects of channel non-linearity, noise, and potential error in the carrier frequency/phase recovery circuits are ignored. There are only two cases to consider during antipodal signaling. In the first, a 0-degree phase offset occurs between R_{k-N }and R_{k}, and in the second, a 180 degree phase offset occurs. If a 0 degree phase offset is transmitted, by definition sample R_{k-N }is equal to sample R_{k}. In this case, computing real(Z_{k}) is identical to computing the power level of the incoming signal, whether the signal levels are positive or negative, because squaring two identical numbers necessarily yields a positive result. With a 180 degree phase offset, the signs of both the incoming I and Q samples are inverted between R_{k-N }and R_{k}, but the absolute value of the magnitude of the I and Q components is otherwise unchanged. Consequently, in a perfect, coherent detection system, during antipodal signaling, the following is true:

power_{k}*=abs*(real(*R*_{k})·real(*R*_{k-N}))+*abs*(imag(*R*_{k})·imag(*R*_{k-N})) (10)

Note the similarity between equation (10) and a restatement of the traditional power estimation function:

power_{k}=real(*R*_{k})·real(*R*_{k})+imag(*R*_{k})·imag(*R*_{k}) (11)

This parallel represents an important observation, for it indicates that the expensive computation of real(Z_{k}) can directly yield a signal power estimate, via two inexpensive absolute value operations, and a single addition. For the purposes of differentiation from standard methods of computing power, this new formulation of signal power is referred to herein as modulation power.

Further examination of real(Z_{k}) yields another interesting observation. During 0-degree phase shifts, real(Z_{k}) is always a large positive number, and during 180 degree phase shifts, real(Z_{k}) is always a large negative number. In other words, the sign of real(Z_{k}) is entirely sufficient to differentiate between the 0-degree and 180-degree phase shifts that characterize antipodal signaling. It is therefore unnecessary to compute imag(Z_{k}) because it yields no additional information beyond that of real(Z_{k}). Consequently, it is possible to compute the differential phase sample Z_{k }for antipodal symbols with one-half of the complexity that is typically required.

This reduction in phase detection to a single sign bit reduces storage requirements for the sequence of sample phases to one bit/sample. This shortens the length of preamble shift register **6** by one-half, and yields corresponding simplifications to the logic which follows it.

As is illustrated in **21**, delay blocks **22***a *and **22***b *yield one-symbol delayed versions of both signals. Multipliers **23***a *and **23***b *compute the partial products of the I and Q samples and the complex conjugate of the delayed signal, yielding the real and imaginary components of real(Z_{k}). An adder **24** sums these phase components to yield a differential phase sample real(Z_{k}). A sign block **25** produces the differential phase bit that flags 0-degree relative phase shifts with a ‘1,’ and 180-degree samples with a ‘0.’These phase bits are sequentially clocked into a preamble shift register **26** in the form of a serially-concatenated phase sequence. The nominal preamble phase sequence **27** is exclusive-ORed with the receive phase sequence by XOR gates **28**. As a minor efficiency enhancement, note that the preamble phase sequence **27** is inverted in this implementation, such that a preamble data pattern of binary 00110011 is represented by the phase bit sequence 1010 instead of 0101.

Power estimation in the preamble detector of **29***a *and **29***b *force these phase components to be positive, and the adder **30** sums them to create a received signal power estimate. The comparator **31** compares the power estimate with the minimum power level **32** necessary for a sample to be considered a valid received signal. As with the preamble detector of **33**, corresponding to one bit per received sample. When a signal sequence has been received which contains the minimum necessary power, and with the correct sample phases, the outputs of the OR gates **34** are all low. The NOR gate **35** detects this condition, and outputs a high level at the preamble detection output **36**, flagging the presence of a new data burst.

Of all the simplifications implemented in **2** from

Because all elements of this preamble detector are derived from the components of Z_{k}, it is sufficient to consider the effect of a rotating constellation on the computation of Z_{k}. The definition of QPSK signaling states that, in the absence of carrier rotation, the magnitude of received signal components I and Q each alternate between:

+/−scale·*sqrt*(2)/2 (12)

where scale is an arbitrary gain value that permits representation of the received signal components in integer form. This factor changes dynamically with changing channel conditions, but may be considered to be a nominal fixed value throughout the duration of an individual symbol. Further, consider initially that the degree of carrier rotation is constant during an individual symbol, such that there exists a unique arbitrary carrier phase offset for each received symbol. In the case of antipodal signaling, modulation power is indistinguishable from conventionally measured power, regardless of the carrier phase. This outcome is not unexpected because, by definition, the absolute magnitude of a transmitted QPSK signal remains constant at all carrier phases as long as it is sampled at the proper symbol timing phase. In the absence of symbol timing recovery, the received power level necessarily varies as zero-crossings occur, but this is as true for conventionally determined power as it is for modulation power.

In the event of a significant carrier frequency error, where the ideal symbol phase slowly rotates each symbol interval, modulation power yields a slight reduction in the estimated power level. The degree of reduction is proportional to the degree of carrier frequency error. For most applications, the error in the modulation power estimate caused by carrier error is inconsequential. For very large carrier errors, QPSK bit error rates rise quickly in the absence of hardware carrier recovery. Therefore, signal power estimation of a base band signal with high carrier frequency error is unlikely to be a performance-limiting factor.

For simplicity of presentation, the discussion thus far has focused solely on antipodal signaling. Incorporating non-antipodal signaling, e.g. symbol values of ‘1’ and ‘2,’ potentially results in a wider range of possible modulation power levels. Given any specific received symbol value, the antipodal symbols have already been discussed. Thus, the question arises of what power estimate is generated during relative symbol phases of +90 and −90 degrees. In a coherent receiver, the modulation power estimator produces results that are essentially identical to conventionally measured power for both antipodal and non-antipodal symbols. However, in differential receivers, the magnitude of the modulation power estimate for non-antipodal symbol transitions varies dependent upon carrier phase error.

Simulation of non-antipodal signaling in the presence of carrier error yields a mean expected modulation power level of approximately 0.6365 times conventional power measurement. Including both antipodal and non-antipodal symbols, a random sequence of QPSK symbols yields a gain calibration factor of approximately 1.222. After calibration, which need only be performed once per data burst, the modulation power estimator may replace conventional signal power measurement for many applications that involve pseudo-random transmitted data. Because many, if not most, data transmission systems already use some form of randomization to improve system performance, the modulation power estimator has broad potential applicability.

The introduction of noise into the received signal does yield a slight divergence between conventional power and modulation power, but over the length of a data burst, modulation power converges with conventional power to only a small degree of error. If increased accuracy is required, simulation may be used to create a simple linear correction factor that reduces the error. Importantly, the specific calibration factor is independent of the signal/noise ratio or the received power level, and is dependent only upon the spectral characteristics of the noise, and the number of samples that are incorporated in the measurement. Consequently, modulation power may be used in most calculations that require a signal power estimator, including preamble threshold detection, absolute signal strength, or the received signal/noise ratio.

Signaling Performance

Thus far, the means have been disclosed to create a high-efficiency preamble detector, but no assessment has yet been made of the signaling performance of the resulting subsystem. In particular, it is well known that coherent QPSK demodulation outperforms differential QPSK demodulation by 2-3 dB. That is, for an equivalent system bit error rate, a coherent detector can function with a 2-3 dB lower Signal/Noise ratio. Therefore, the choice of differential detection may appear to have introduced performance degradation into the selected preamble detector. Surprisingly, the core methodology outlined herein of using real(Z_{k}) for phase detection of antipodal signaling actually outperforms theoretically perfect coherent demodulation of random QPSK data by 3 dB, assuming proper symbol timing recovery. This unexpected outcome may be understood by realizing that during antipodal signaling, the I and Q waveform components reinforce one another. For an error to occur, the amplitude of a noise peak must necessarily be twice as large to result in a sign change of the summed I and Q phase components, as compared to non-antipodal signaling. Alternately, antipodal signaling during a preamble may be viewed as a halving of the transmitted bandwidth because the I and Q components carry identical information. Consequently, a 3 dB gain is to be expected.

However, for efficiency purposes, the preferred implementation of the preamble detector does not perform symbol timing recovery. Instead, a binary mask is used to remove those samples that are performing zero-crossings. In this context, it is apparent that a signal that exhibits either a 0-degree or 180-degree symbol timing offset from the transmitter yields the full 3 dB of improvement over a traditional coherent QPSK data detector. From examination of the square-root raised cosine pulse shape that is most commonly used for data transmission systems, it becomes clear that a worst-case reduction in the amplitude of real(Z_{k}) using this masking approach in a two sample/symbol receiver occurs at a symbol timing error of +/−90 degrees. In this case, the amplitude of real(Z_{k}) is precisely one-half of the amplitude without symbol timing error. Because a 50% reduction in signal amplitude is equivalent to a 3 dB loss, this indicates that the worst-case performance of this differential preamble detector exactly matches the theoretical performance of a coherent demodulator. Integration over all possible symbol timing offsets yields a mean expected amplitude for real(Z_{k}) that is approximately 1.786 times higher than that of an individual I or Q component, resulting in a net signal/noise ratio improvement of 2.5 dB over a theoretically perfect coherent QPSK detector for random QPSK data. Realistically, this means that the preferred implementation always outperforms the QPSK data demodulator that follows it, whether it is a coherent detector, or a differential detector. In other words, the selected architecture does not introduce any meaningful performance degradation.

While not revealed previously, the initial implementation of the disclosed invention is in a multi-user transmission system, where multiple transmitters share a common transmission frequency. The frequency is shared via time-multiplexing the data bursts from the individual transmitters. In this specific implementation, no carrier sense mechanism is used by the transmitters to detect when the shared frequency is already in use, leading to collisions where the data bursts from different transmitters sometimes overlap. This environment places an even greater burden upon the preamble detection system. Unlike single-user systems, in a multi-user system it is possible to encounter full-power random data transmission immediately following a collision. When this occurs, the preamble detector must differentiate between all four QPSK states, rather than benefiting from the known structure of antipodal preamble signaling preceding each data burst. Consequently, it may appear as though the computation of a single phase vector real(Z_{k}) in place of the full complex phase vector Z_{k }would yield performance deterioration. However, consider again the formula for the imaginary component of Z_{k}:

imag(*Z*_{k})=real(*R*_{k})·imag(*R*_{k-N})+imag(*R*_{k})·real(*R*_{k-N}) (13)

While it was previously postulated that removal of imag(Zk) was possible for the detection of antipodal signaling, this is now examined in more detail. In the absence of noise, the value of imag(Z_{k}) during antipodal signaling has a small amplitude relative to real(Z_{k}). Conversely during non-antipodal signaling, the value of imag(Z_{k}) alternates between a large positive and large negative amplitude, while the value of real(Z_{k}) has a small relative amplitude. Therefore, even when the enhanced efficiency preamble detector encounters truly random QPSK data containing both antipodal and non-antipodal symbols, the power threshold detection means ensures that non-antipodal signal transitions are not incorrectly identified as valid antipodal preamble transitions. In both single-user and multi-user environments, the proposed preamble detector properly differentiates antipodal preamble symbol transitions.

Exemplary Preamble Detector

The following is a code listing of the logic for a preamble detector used in a high-density return path receiver. The listing is provided for purposes of example and is for use with the MIPS family of processors.

Although the invention is described herein with reference to the preferred embodiment, one skilled in the art will readily appreciate that other applications may be substituted for those set forth herein without departing from the spirit and scope of the present invention. Accordingly, the invention should only be limited by the claims included below.

## Claims

1. A preamble detector for QPSK, comprising:

- an input for receiving digitized input I and Q samples, wherein said input I and Q samples represent a reconstructed base band form of QPSK modulation;

- a carrier derotation means for aligning said incoming signal phases with I and Q axes;

- sign means for producing a ‘1’ if said I and Q samples are greater than or equal to 0, or a ‘0’ if said samples are less than 0;

- sample delay means for providing chains of N-sample delays to yield one symbol-length delay for both I and Q;

- a differential decoder for combining a current symbol state with a prior symbol state to yield a differentially decoded symbol value;

- a multiplexer for alternating between a least-significant and a most-significant bit of said differentially decoded symbol values; and

- a preamble shift register containing a serial-sequential representation of a received data stream.

2. The detector of claim 1:

- wherein said shift register length is twice a number of bits in a preamble; and

- wherein binary data bits are clocked into said preamble shift register at two bits/sample.

3. The detector of claim 2, said shift register further comprising:

- XOR means for locating a unique preamble data pattern in accordance with the following: Preamble_Mismatch=Preamble_Register XOR PREAMBLE_PATTERN

- wherein said PREAMBLE_PATTERN is a bit-pair doubled representation of a unique data pattern that defines an implementation-specific value for said preamble;

- wherein Preamble_Mismatch indicates outputs of said XOR means;

- wherein said XOR means invert any bits in said preamble that should be a binary ‘1;’ and

- wherein when outputs of said XOR means all become zero, indicating no mismatch, a data pattern has been identified that matches a desired preamble data pattern.

4. The detector of claim 3, further comprising:

- means for producing a value of modulation power, where: powerk=abs(real(Rk)·real(Rk-N))+abs(imag(Rk)·imag(Rk-N)).

5. The detector of claim 3, further comprising:

- a comparator for comparing said signal power level to a predetermined minimum acceptable power threshold;

- wherein an output of said comparator is a ‘1’ if an input signal level is too low to be considered a valid transmission, and said comparator output is ‘0’ if said power level exceeds said threshold;

- a Power_Invalid shift register which receives said comparator output, said Power_Invalid shift register containing a history of an invalidity status of recent samples; and

- OR means for merging Power_Invalid flags with Preamble_Mismatch outputs, resulting in a product expression of: Preamble_Status=Preamble_Mismatch OR Power_Invalid

- wherein a candidate preamble has both a proper bit polarity and a proper signal level; and

- wherein said OR means combine said I and Q data bits, whereby if either of said I or Q samples have incorrect signs, then an output of that sample from said OR means becomes true to indicate a non-matching symbol.

6. The detector of claim 5, further comprising:

- AND means for isolating N-1 out of N samples to ignore one sample/symbol during which zero-crossings may occur;

- wherein with two samples/symbol, said AND means isolates alternate samples.

7. The detector of claim 6, further comprising:

- NOR means;

- wherein once all relevant samples have proper signs, and have been received with a sufficient power level, an output of said NOR means is driven high, indicating Preamble_Found;

- wherein said detector begins the process of receiving a new data burst.

8. The detector of claim 1, wherein, if a preamble used is an unchanging constant, said detector further comprising:

- NOT means inserted selectively at any sample timing offset where an expected value of a preamble is ‘1.’

9. The detector of claim 1, wherein said shift register is extendable to use said detector with any integer number of samples/symbol, or any preamble length.

10. A preamble detection method for QPSK, comprising the steps of:

- receiving digitized input I and Q samples, wherein said input I and Q samples represent a reconstructed base band form of QPSK modulation;

- aligning said incoming signal phases with I and Q axes;

- producing a ‘1’ if said I and Q samples are greater than or equal to 0, or a ‘0’ if said samples are less than 0;

- providing chains of N-sample delays to yield one symbol-length delay for both I and Q;

- combining a current symbol state with a prior symbol state to yield a differentially decoded symbol value;

- alternating between a least-significant and a most-significant bit of said differentially decoded symbol values; and

- providing a serial-sequential representation of a received data stream.

11. The detection method of claim 10:

- wherein said serial-sequential representation of a received data stream length is twice a number of bits in a preamble; and

- wherein binary data bits are clocked in at two bits/sample.

12. The detection method of claim 11, further comprising the step of:

- locating a unique preamble data pattern in accordance with the following: Preamble_Mismatch=Preamble_Register XOR PREAMBLE_PATTERN

- wherein said PREAMBLE_PATTERN is a bit-pair doubled representation of a unique data pattern that defines an implementation-specific value for said preamble;

- wherein Preamble_Mismatch indicates an XOR output;

- wherein any bits in said preamble that should be a binary ‘1’ are inverted; and

- wherein when said XOR output becomes zero, indicating no mismatch, a data pattern has been identified that matches a desired preamble data pattern.

13. The detection method of claim 12, further comprising the step of:

- implementing a power estimation function;

- producing a value of modulation power, where: powerk=abs(real(Rk)·real(Rk-N))+abs(imag(Rk)·imag(Rk-N)).

14. The detection method of claim 12, further comprising the steps of:

- comparing said signal power level to a predetermined minimum acceptable power threshold;

- wherein an output of said comparing step is a ‘1’ if an input signal level is too low to be considered a valid transmission, and said comparing step output is ‘0’ if said power level exceeds said threshold;

- receiving said comparing step output a Power_Invalid shift register, said Power_Invalid shift register containing a history of an invalidity status of recent samples; and

- merging Power_Invalid flags with Preamble_Mismatch outputs, resulting in a product expression of: Preamble_Status=Preamble_Mismatch OR Power_Invalid

- wherein a candidate preamble has both a proper bit polarity and a proper signal level; and

- wherein said merging step combines said I and Q data bits, whereby if either of said I or Q samples have incorrect signs, then an output of that sample from said merging step becomes true to indicate a non-matching symbol.

15. The detection method of claim 14, further comprising the step of:

- isolating N-1 out of N samples to ignore one sample/symbol during which zero-crossings may occur;

- wherein with two samples/symbol, alternate samples are isolated.

16. The detection method of claim 15, wherein once all relevant samples have proper signs, and have been received with a sufficient power level, an output is driven high, indicating Preamble_Found;

- wherein said detector begins the process of receiving a new data burst.

17. The detection method of claim 10, wherein, if a preamble used is an unchanging constant, said detector further comprising the step of:

- inserting a NOT function selectively at any sample timing offset where an expected value of a preamble is ‘1.’

18. The detection method of claim 10, further comprising the step of:

- extending said detector with any integer number of samples/symbol, or any preamble length.

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**Patent History**

**Patent number**: 7428273

**Type:**Grant

**Filed**: Sep 16, 2004

**Date of Patent**: Sep 23, 2008

**Patent Publication Number**: 20050063493

**Assignee**: Promptu Systems Corporation (Menlo Park, CA)

**Inventor**: Mark J. Foster (Palo Alto, CA)

**Primary Examiner**: Ted Wang

**Attorney**: Glenn Patent Group

**Application Number**: 10/944,503

**Classifications**

**Current U.S. Class**:

**Phase Shift Keying (375/329);**Phase Shift Keying (375/279); Phase Shift Keying (375/308); Particular Demodulator (375/324); Including Coherent Detector (375/325); Particular Pulse Demodulator Or Detector (375/340)

**International Classification**: H03D 3/22 (20060101); H04L 27/22 (20060101);